1. Field
This invention relates to a semiconductor apparatus that is applicable to an active element, such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), and a bipolar transistor, and to a passive element, such as a diode, and that which can achieve both higher breakdown voltage and higher current capacity.
2. Description of Related Art
In general, a semiconductor apparatus is classified as a horizontal element having an electrode formed on one surface of a semiconductor substrate or as a vertical element having electrodes on both surfaces of a semiconductor substrate. In the vertical semiconductor apparatus, the direction of flow of a drift current in an on-state is the same as the direction of extension of a depletion layer caused by reverse bias voltage in an off-state. In an ordinary planar n-channel vertical MOSFET, a portion serving as a high-resistance n− drift layer works as a region that causes drift current to flow vertically in the on-state. Shortening a current path in the n− drift layer, therefore, reduces drift resistance, offering an effect of reducing the substantial on-resistance of the MOSFET.
The portion serving as the high-resistance n−-drift layer, however, is depleted of carriers in the off-state, increasing breakdown voltage. If the n−-drift layer is thinned, the expansion of a drain-base depletion layer that starts from the pn-junction between a P-base region and the n−-drift layer becomes smaller in width, causing the MOSFET to quickly reach a critical electric field, which reduces breakdown voltage. Conversely, a semiconductor apparatus with high breakdown voltage has a thicker n−-drift layer, which increases on-resistance, inviting greater loss. In this manner, on-resistance and breakdown voltage have a mutual relationship of trade-off.
It is known that this trade-off relationship exists in a similar manner in such a semiconductor apparatus as an IGBT, a bipolar transistor, and a diode. The trade-off relationship is also commonly observed in a horizontal semiconductor apparatus in which the direction of flow of the drift current in the on-state is different from the direction of expansion of the depletion layer caused by reverse bias.
A superjunction semiconductor apparatus is known as a solution to a problem posed by the trade-off relationship. This superjunction semiconductor apparatus includes a drift layer that is composed of a parallel pn-structure with enhanced impurity concentration constructed by repeatedly joining alternately arranged n-regions and p-regions (see, e.g., Patent Documents 1, 2 and 3). According to the semiconductor apparatus having such a structure, although the parallel pn-structure has high impurity concentration, a depletion layer expands laterally from vertically extending pn-junctions of the parallel pn-structure to be depleted of carrier in the entire drift layer, which achieves high breakdown voltage.
To achieve the high breakdown voltage of a semiconductor apparatus, a peripheral structure is needed. A lack of the peripheral structure results in a drop in breakdown voltage at the termination of a drift layer, which makes achieving high breakdown voltage difficult. To solve this problem, a structure has been proposed that at the peripheral region, another parallel pn-structure with smaller repetition pitch than that of the parallel pn-structure in the active region is disposed in a region closer to the surface of the active region (see, e.g., Patent Document 4). According to the proposed structure, a surface electric field near the outermost active region is eased to maintain high breakdown voltage.
A semiconductor apparatus has been proposed, which includes a first-conductive (n-type) first semiconductor layer, a first-conductive (n-type) first semiconductor pillar region formed on a main surface of the first semiconductor layer, a second-conductive (p-type) second semiconductor pillar region that is formed on the main surface of the first semiconductor layer in adjacent to the first semiconductor pillar region so that the second semiconductor pillar region and the first semiconductor pillar region jointly form a periodic arrangement structure in a direction substantially parallel to the main surface of the first semiconductor layer, a first-conductive (n-type) second semiconductor layer formed above the first semiconductor layer at the peripheral region having an impurity concentration lower than the impurity concentration of the first semiconductor pillar region, and an embedded guard ring layer made of a second-conductive (p-type) semiconductor that is selectively embedded in the second semiconductor layer (see, e.g., Patent Document 5).
A semiconductor apparatus has been proposed, which includes a RESURF layer formed on the surface of a semiconductor intermediate layer in a peripheral region, a termination contact semiconductor region formed on the part of the RESURF layer surface that is closer to an active region, a field oxide film formed on the RESURF layer surface that has a thickness thinner on the portion closer to the active region while thicker on the portion farther in the opposite direction to the active region, and a field plate extending from the surface of the termination contact semiconductor region to pass over the thin part of the field oxide film to reach the surface of the thick part of the field oxide film (see, e.g., Patent Document 6).
A semiconductor apparatus has been proposed, which includes a peripheral structure having a parallel pn-structure constructed by repeatedly joining alternately arranged vertical first-conductive (n-type) regions oriented in the direction of thickness of a substrate and vertical second-conductive (p-type) regions oriented in the direction of thickness of the substrate and a field plate formed on an insulating film on a first main surface of the peripheral structure, where in the parallel pn-structure, the impurity concentration at the first main surface side of the vertical second-conductive (p-type) regions located outside a leading edge of the field plate is higher than the impurity concentration at the first main surface side of the second vertical first-conductive (n-type) regions adjacent to the second-conductive (p-type) regions (see, e.g., Patent Document 7).
A semiconductor apparatus has been proposed, which includes a first-conductive (n-type) pillar region formed along a direction parallel to semiconductor substrate and a peripheral structure having a second-conductive (p-type) semiconductor region formed to encircle an active region and extend from the active region to the first-conductive (n-type) pillar region, wherein a first-conductive (n-type) semiconductor region is formed in the second-conductive (p-type) semiconductor region, and average impurity concentration given by subtracting the average impurity concentration of the first-conductive (n-type) semiconductor region from the average impurity concentration of the second-conductive (p-type) semiconductor region is determined to be 2.5*1014 cm−3 or less (see, e.g., Patent Document 8).
A semiconductor apparatus has been proposed in the form of a power MOSFET having a superjunction structure in which the impurity concentration of a p-RESURF layer has a distribution (gradient profile) of reducing the impurity concentration in the direction of depth, which distribution suppress the breakdown voltage drop caused by the imbalance between the impurity volume of the p-RESULF layer and the impurity volume of an n−-drift layer more significantly than in a conventional case (see, e.g., Patent Document 9).
Below is a list of related art publications:
                Patent Document 1: U.S. Pat. No. 5,216,275        Patent Document 2: U.S. Pat. No. 5,438,215        Patent Document 3: Japanese Laid-Open Patent Publication No. H9-266311        Patent Document 4: Japanese Laid-Open Patent Publication No. 2003-224273        Patent Document 5: Japanese Laid-Open Patent Publication No. 2008-4643        Patent Document 6: Japanese Laid-Open Patent Publication No. 2007-5516        Patent Document 7: Japanese Laid-Open Patent Publication No. 2003-204065        Patent Document 8: Japanese Laid-Open Patent Publication No. 2007-335658        Patent Document 9: Japanese Laid-Open Patent Publication No. 2004-119611        
For conventional semiconductor apparatuses as discussed and noted above, the robustness against charges on breakdown voltage is not taken into consideration. A semiconductor apparatus having low robustness against charges manages to secure initial breakdown voltage but gradually loses its breakdown voltage as time elapses, which poses a problem of difficulty in ensuring breakdown voltage reliability. For example, the semiconductor apparatus disclosed in the Patent Document 5 has no parallel pn-layer under an n−-layer of the peripheral structure, which poses a problem of difficulty in achieving high breakdown voltage. The semiconductor apparatus disclosed in the Patent Document 6 has no n−-layer on the surface of the peripheral structure, which poses a problem that securing breakdown voltage is difficult when negative charges are present at the surface of the peripheral structure. The semiconductor apparatus disclosed in the Patent Document 7 poses a problem that electric field concentration occurs at a stopper electrode, deteriorating breakdown voltage when negative charges are present at the surface of the peripheral structure. The semiconductor apparatus disclosed in the Patent Document 8 poses a problem that with the termination working actually as the second-conductive (p-type) termination, charge imbalance toward the second-conductive type (p-type) causes the breakdown voltage of the peripheral region to become lower than that of the active region.
FIG. 54 is a diagram of the simulation results of robustness against surface charges on breakdown voltage in a conventional semiconductor apparatus. These simulation results are obtained with regard to the semiconductor apparatus disclosed in the Patent Document 4 (FIGS. 17 to 19). As depicted in FIG. 54, the presence of positive charges (positive ions) on an oxide film between a field plate electrode and a channel stopper electrode results in a drop in breakdown voltage. This happens because of the following reason. In the semiconductor apparatus disclosed in the Patent Document 4, a parallel pn-layer having a narrow structural pitch and low impurity concentration is disposed closer to the semiconductor surface in the peripheral region. This parallel pn-layer allows a depletion layer to easily expand, thus relaxing an electric field strength at a field plate end to enable higher breakdown voltage. The presence of positive charges (positive ions) on the oxide film of the peripheral region, however, makes expansion of the depletion layer difficult, thus causing an electric field at the field plate end to intensify. As a result, breakdown voltage drops.
FIGS. 55 to 57 depict electric potential distributions of an off-state in the conventional semiconductor apparatus. FIG. 55 depicts the electric potential distribution in the case that a surface charge quantity on the oxide film of the peripheral region is −1.0*1012 cm2. FIG. 56 depicts the electric potential distribution in the case that the surface charge quantity is 0.0 cm−2. FIG. 57 depicts the electric potential distribution in the case that the surface charge quantity is +1.0*1012 cm−2. These figures reveal that the depletion layer expands sufficiently between the filed plate electrode and the channel stopper electrode when charges are negative charges (negative ions) but the depletion layer concentrates on the field plate end when surface charges are positive charges (positive ions). In FIGS. 55 to 57, intervals between electric potential lines represent 50 V (as in FIGS. 10 to 12, 20 to 22, and 31 to 33).
This invention was conceived to solve the problems posed by the conventional ones, and it is therefore an object of embodiments of this invention to provide a semiconductor apparatus capable of improving robustness against charges on breakdown voltage.